View ADP2390-EVALZ_8867877.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

18 v, 12 a step - down regulator with programmable current limit data sheet adp2389 / adp2390 features input voltage : 4.5 v to 18 v continuous output current: 12 a integrated mosfet s : 17 m high - side / 4. 5 m low - side 0.6 v 0.5 % reference voltage programmable sw itching frequency range: 200 khz to 2 2 00 k hz enhanced transient response programmable current li mit with 10% accuracy precision enable and power good external compensation and soft start pfm m ode ( adp2390 only) start up into a precharged output supported by the adisimpower design tool applications communication infrastructure networking and servers industrial and instrumentation healthcare and medical intermediate power rail conversion s dc - to - dc point of load application s typical applications circuit figure 1. general description the adp2389 / adp2390 are current mode control, synchronou s s tep - down , dc - to - dc regulator s . they integrate a 17 m? high - side power mosfet and a 4. 5 m? synchronous rectifier mosfet to provide a high efficiency solution. the adp2390 operate s in pulse frequency modulation (pfm) mode to improve the system efficiency at light load. the adp2389 / adp2390 run from an input voltage of 4.5 v to 18 v and can deliver up to 12 a of output current. the output voltage can be adjusted to 0.6 v and the switching frequency can be programmed between 200 khz to 2 2 00 k hz. the adp2389 / adp2390 target high performance applications that require high efficie ncy and design flexibility. external c ompensation and soft start provide design flexibility. the power - g ood output and precision enable input provide simple and reliable power sequencing. an e nhanced tra nsient response feature improves the load transient p erformance , which reduce s the output capacitance. programmable current limit allows the user t o optimized the inductor design and provide a compact solution. other key features include undervoltage lockout (uvlo) , overvoltage protection ( ovp ) , overcurrent protection ( ocp ) , and thermal shutdown (tsd) . the adp2389 / adp2390 operates over a ? 40 c to +125 c junction temperature ran ge and is available in 32 - lead , 5 mm 5 mm lfcsp package. figure 2. adp2389 efficiency vs. output current, v in = 12 v, f sw = 300 khz bst fb comp pgood gnd vreg rt ilim ftw ss l c vreg r t r ilim r ftw sw pgnd en pvin vin c in v in c bst c out v out r top r bot c c r c c ss adp2389/ adp2390 12192-001 100 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 7 8 9 10 11 12 efficiency (%) output current (a) v out = 1.2v v out = 1.8v v out = 3.3v v out = 5.0v 12192-002 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibili ty is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any pa tent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog d evices, inc. all rights reserved. technical support www.analog.com
adp2389/adp2390 data sheet rev. 0 | page 2 of 23 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? typical applications circuit ............................................................ 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? detailed functional block diagram .............................................. 3 ? specifications ..................................................................................... 4 ? absolute maximum ratings ............................................................ 6 ? thermal information ................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? theory of operation ...................................................................... 12 ? control scheme .......................................................................... 12 ? pfm mode (adp 2390 only) .................................................... 12 ? precision enable/shutdown ...................................................... 12 ? internal regulator (vreg) ....................................................... 12 ? bootstrap circuitry .................................................................... 12 ? oscillator ..................................................................................... 12 ? soft start ...................................................................................... 13 ? fast transient response ............................................................ 13 ? power good ................................................................................. 13 ? peak current-limit and short-circuit protection ................. 13 ? overvoltage protection (ovp) ................................................. 13 ? undervoltage lockout (uvlo) ............................................... 13 ? thermal shutdown .................................................................... 13 ? applications information .............................................................. 14 ? input capacitor selection .......................................................... 14 ? output voltage setting .............................................................. 14 ? inductor selection ...................................................................... 14 ? output capacitor selection....................................................... 15 ? programming input voltage uvlo ........................................ 15 ? compensation design ............................................................... 15 ? design example .............................................................................. 17 ? output voltage setting .............................................................. 17 ? frequency setting ....................................................................... 17 ? inductor selection ...................................................................... 17 ? output capacitor selection....................................................... 17 ? compensation components ..................................................... 18 ? soft start time program ........................................................... 18 ? input capacitor selection .......................................................... 18 ? schematic for design example ................................................. 18 ? external components recommendation .................................... 19 ? circuit board layout recommendations ................................... 20 ? typical application circuits ......................................................... 22 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 23 ? revision history 8/15revision 0: initial version
data sheet adp2389/adp2390 rev. 0 | page 3 of 23 detailed functional block diagram figure 3. adp2389 / adp2390 detailed functional block diagram control logic and mosfet driver with anticross protection i max hiccup mode + ? + 0.6v i ss ss fb comp g m ftw ocp cmp + ? ? + + ? i neg + ? negative current comparator bst pvin v re g 5v regulator sw nfet nfet vreg pgnd driver driver deglitch pgood gnd en_buf en 1.2v 1.3a ilim clk slope ramp rt osc ocp threshold setting fast transient window 4.8a skip cmp adp2390 only pfm threshold slope ramp ? + ovp 0.7v ? + 0.66v ? + 0.54v clk a cs + ? shutdown logic thermal shutdown uvlo boost regulator vin adp2389/adp2390 12192-003
adp2389/adp2390 data sheet specifications v pvin = v vi n = 12 v, t j = ? 40 c to + 125 c for min imum /max imum specifications, and t a = 25c for typical specification s , unless otherwise noted. table 1 . parameter symbol test conditions/comments min typ max units s upply v o ltage (pvin and vin ) pvin voltage range v pvin 4.5 18 v vin voltage range v vin 4.5 18 v quiescent current i q no s witching 1 .16 1.5 ma shutdown current i shdn en = gnd 7.5 2 0 a vin under voltage lockout threshold uvlo vin rising 4.2 4.4 v vin falling 3.5 3.7 v feedback (fb ) fb regulation voltage v fb 0 c < t j < 85 c 0.597 0.6 0.603 v ?40c < t j < + 125 c 0.594 0.6 0.606 v fb bias current i fb 0.01 0.1 a error amplifier (ea) trans c onductance g m 450 500 550 s ea source current i source 40 50 60 a ea sink current i sink 40 50 60 a i nternal r egulator (vreg) vreg voltage v vreg i vreg = 10 ma 4.8 5 5.2 v dropout voltage i vreg = 50 ma 3 55 mv regulator current l imit 100 ma switch node ( sw ) on resistance 1 high - side r dson_h v boot = 5 v 17 30 m low - side r dson_l v vreg = 5 v 4. 5 9 m sw min imum on time 2 t min_on 100 ns sw min imum off time 2 t min_o ff 150 ns current limit ilim voltage v ilim 0.592 v ilim current range i ilim 1.8 12 a high - side peak current limit i ocp r ilim = 59 k 15 16.8 18.6 a low - side negative current limit 2 4 a bst bootstrap voltage v b oot 4.6 5 5.4 v oscil l ator (rt ) switching frequency f sw r t = 100 k 540 600 660 khz switching frequency range 200 2200 khz f ast transient window (ftw) fast t ransient r esponse w indow r ftw = 100 k 2 % min imum fast t ransient r esponse w indow 2 1 % ss ss pin pull -u p current i ss 2.7 3.4 4.1 a rev. 0 | page 4 of 23
data sheet adp2389/adp2390 parameter symbol test conditions/comments min typ max units pgood fb threshold rising 106 110 114 % falling 86 90 94 % fb hysteresis rising 5 % falling 5 % power - good deglitch time pgood from low to high 16 cycle s pgood from high to low 16 cycle s pgood leakage current v pgood = 5 v 0.01 0. 1 a pgood output low voltage i pgood = 1 ma 150 260 mv en en rising threshold 1.2 1.28 v en falling threshold 1.02 1.1 v en source current en voltage < 1.1 v 6.1 a en voltage > 1.2 v 1 .3 a thermal thermal shutdown threshold 150 c thermal shutdown hysteresis 25 c 1 pin - to - p in m easurement . 2 guaranteed by design. rev. 0 | page 5 of 23
adp2389/adp2390 data sheet rev. 0 | page 6 of 23 absolute maximum ratings table 2. parameter rating pvin, vin, en, pgood ?0.3 v to +22 v sw ?1 v to +22 v bst v sw + 6 v fb, ss, comp, rt, ilim, ftw, vreg ?0.3 v to +6 v pgnd to gnd ?0.3 v to +0.3 v operating junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j-std-020 stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. unless otherwise specified, all other voltages are referenced to gnd. thermal information ja is specified for the worst-case conditions, that is, a device soldered in a circuit board (4-layer, jedec standard board) for surface-mount packages. table 3. thermal resistance package type ja jc unit 32-lead lfcsp 41 2.2 c/w esd caution
data sheet adp2389/adp2390 rev. 0 | page 7 of 23 pin configuration and fu nction descriptions figure 4. pin configuration (top view) table 4. pin function descriptions pin no. mnemonic description 1 ss soft start control. connect a capacitor from the ss pin to gnd to program the soft start time. 2 comp error amplifier output. connect an rc network from the comp pin to gnd. 3 fb feedback voltage sense input. connect this pi n to a resistor divider from the output voltage, v out . 4 vreg output of the internal 5 v regulator. the control circuits are powered from this voltage. place a 1 f, x7r or x5r ceramic capacitor between this pin and gnd. 5 gnd analog ground. 6 to 11, 19, 20 sw switch node. connect this pin to an inductor. 12 to 18 pgnd power ground. return of the low-side mosfet. 21 bst supply rail for the high-side gate drive. place a 0.1 f, x7r or x5r capacitor between sw and bst. 22 to 26 pvin power input. connect pvin to the input power source and connect a bypass capacitor between this pin and pgnd. 27 vin power input for control circuitry. bypass vin to gnd with a low equivalent series resistance (esr) capacitor as close to the device as possib le. connect vin to pvin directly. 28 en precision enable. use an external resistor divider to set the turn on threshold. to enable the device automatically, connect the en pin to pvin. 29 ftw fast transient response window setting. connect a resistor between the ftw pin and gnd to set the fast transient response window. 30 pgood power-good output (open-drain). connecting a 10 k to 100 k pull-up resistor from pgood to a pull-up voltage is recommended. 31 ilim current-limit threshold setting. connect a resistor from the ilim pin to gnd to program the current-limit threshold. 32 rt frequency setting. connect a resistor between the rt pin and gnd to program the switching frequency between 200 khz to 2.2 mhz. 33 ep, gnd exposed gnd pad. the exposed gnd pad must be soldered to a large, ex ternal, copper gnd plane to reduce thermal resistance. 34 ep, sw exposed sw pad. the exposed sw pad must be connected to the sw pins by using short, wide traces, or soldered to a large, external, copper sw plane to reduce thermal resistance. 3 3 g n d 3 4 s w a dp2389/adp2390 top view (not to scale) 1 2 3 4 5 6 7 8 s s c o m p f b v r e g g n d s w s w s w 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 s w s w s w p g n d p g n d p g n d p g n d p g n d 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 r t i l i m p g o o d f t w e n v i n p v i n p v i n 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p v i n p v i n p v i n b s t s w s w p g n d p g n d notes 1. the exposed gnd pad must be soldered to a large, external, copper gnd plane to reduce thermal resistance. 2. the exposed sw pad must be connected to the sw pins by using short, wide traces, or soldered to a large, external, copper sw plane to reduce thermal resistance. 12192-004
adp2389/adp2390 data sheet typical performance characteristics t a = 25 c, v pvin = v v in = 12 v, v out = 1.8 v, l = 1 h, c out = 5 100 f, f sw = 5 00 khz, unless otherwise noted. figure 5. adp2389 efficiency at v pv i n = 12 v, f sw = 600 khz figure 6. adp2390 efficiency at v pv i n = 12 v, f sw = 600 khz figure 7 . shutdown current (i shdn ) vs. input voltage figure 8. adp2389 efficiency at v pvi n = 12 v, f sw = 300 khz figure 9. adp2390 efficiency at v pv i n = 12 v, f sw = 300 khz figure 10 . quiescent current (i q ) vs. input voltage 100 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 7 8 9 10 11 12 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5.0v inductor: 744 333 0100 12192-005 100 60 65 70 75 80 85 90 95 0.1 1 10 efficiency (%) output current (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5.0v inductor: 744 333 0100 12192-006 16 0 2 4 6 8 10 12 14 4 6 8 10 12 14 16 18 shutdown current (a) input voltage (v) t j = C40c t j = +25c t j = +125c 12192-007 100 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 7 8 9 10 11 12 efficiency (%) output current (a) v out = 1.2v v out = 1.0v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5.0v inductor: 744 333 0220 12192-008 100 60 65 70 75 80 85 90 95 0.1 1 10 efficiency (%) output current (a) v out = 1.2v v out = 1.0v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5.0v inductor: 744 333 0220 12192-009 1.25 1.00 1.05 1.10 1.15 1.20 4 6 8 10 12 14 16 18 quiescent current (ma) input voltage (v) t j = C40c t j = +25c t j = +125c 12192-010 rev. 0 | page 8 of 23
data sheet adp2389/adp2390 figure 11 . vin uvlo threshold vs. temperature figure 12 . ss pin pull - up current vs. temperature figure 13 . frequency vs. temperature figure 14 . en threshold vs. temperature figure 15 . feedback voltage vs. temperature figure 16 . vreg voltage vs. temperature 4.5 3.6 3.7 3.8 4.0 4.2 4.4 3.9 4.1 4.3 C40 C20 0 20 40 60 80 100 120 vin uvlo threshold (v) temperature (c) falling rising 12192-0 1 1 3.55 3.25 3.30 3.40 3.45 3.50 3.35 C40 C20 0 20 40 60 80 100 120 ss pull-up current (a) temperature (c) 12192-012 620 570 580 600 610 590 C 40 C20 0 20 40 60 80 100 120 frequency (khz) temperature ( c) r t = 100k 12192-013 1.25 0.95 1.00 1.10 1.15 1.20 1.05 C40 C20 0 20 40 60 80 100 120 en threshold (v) temperature (c) rising falling 12192-014 606 594 596 600 602 604 598 C40 C20 0 20 40 60 80 100 120 feedback voltage (mv) temperature ( c) 12192-015 5.3 4.7 4.8 5.0 5.1 5.2 4.9 C40 C20 0 20 40 60 80 100 120 vreg voltage (v) temperature ( c) 12192-016 rev. 0 | page 9 of 23
adp2389/adp2390 data sheet figure 17 . mosfet r dson vs. temperature figure 18 . ea transconductance vs. temperature figure 19 . pfm mode waveform ( adp2390 ) figure 20 . peak current - limit threshold vs. temperature figure 21 . continuous conduction mode (ccm) waveform figure 22 . soft start with full load 30 0 5 15 20 25 10 C40 C20 0 20 40 60 80 100 120 mosfet r dson (m) temperature (c) high-side r dson low-side r dson 12192-017 520 470 480 500 510 490 C40 C20 0 20 40 60 80 100 120 ea transconductance (s) temperature (c) 12192-018 1 2 4 t ch1 50.0mv b w ch2 10.0v ch4 2.00a b w m 100s a ch1 C2.00mv t 50.20% v out (ac) i l sw 12192-019 18.0 15.0 15.5 16.5 17.0 17.5 16.0 C40 C20 0 20 40 60 80 100 120 peak current-limit threshold (a) temperature (c) r ilim = 59k 12192-020 1 2 4 t ch1 10.0mv b w ch2 10.0v ch4 5.00a m 2.00s a ch2 5.40v t 50.20% i l v out (ac) sw 12192-021 ch1 1.00v b w ch2 10.0v b w ch3 5.00v b w ch4 10.0a b w m1.00ms a ch1 1.08v t 50.00% 1 2 4 3 t v out en i out pgood 12192-022 rev. 0 | page 10 of 23
data sheet adp2389/adp2390 figure 23 . precharged output figure 24 . load transient response with fast transient enable, i out = 2.4 a to 9.6 a figure 25 . output short entry figure 26 . load transient response, i out = 2.4 a to 9.6 a figure 27 . line transient response, v pvi n from 8 v to 14 v, i out = 12 a figure 28 . output short recovery ch1 1.00v b w ch2 10.0v b w ch3 5.00v b w ch4 5.00a b w m1.00ms a ch3 2.90v t 50.40% 1 2 4 3 t v out en i l pgood 12192-023 ch1 50.0mv b w ch4 5.00a b w m 200s a ch4 6.00a t 20.00% 1 4 t v out (ac) i out 12192-024 ch1 1.00v b w ch2 10.0v b w ch4 10.0a b w m1.00ms a ch1 1.08v t 20.20% 1 2 4 t v out sw i l 12192-025 ch1 50.0mv b w ch4 5.00a b w m 200s a ch4 4.90a t 20.00% 1 4 t v out (ac) i out 12192-026 ch1 10.0mv b w ch2 10.0v b w ch3 5.00v b w m1.00ms a ch3 11.0v t 20.40% 1 2 3 t v out (ac) sw pvin 12192-027 ch1 1.00v b w ch2 10.0v b w ch4 10.0a b w m10.0ms a ch1 1.06v t 80.20% 1 2 4 t v out sw i l 12192-028 rev. 0 | page 11 of 23
adp2389/adp2390 data sheet theory of operation the adp2389 / adp2390 are synchronous step - down, dc - to - dc regulator s. the se devices use a current - mode control architecture with an integrated high - side power switch and a low - side synchro - nous rectifier. the regulator s target high performance applications that require high efficiency and design flexibility. the adp2389 / adp2390 can operate with an input voltage from 4.5 v to 18 v and can regulate the output voltage to 0. 6 v. addi - tional features added for design flexibility include programmable switching frequency, programmable soft start, programmable current limit, external compensation, precision enable, and a power - good output. control scheme the adp2389 / adp2390 use a fixed frequency, peak current mode pulse - width modulation ( pwm ) control architecture. at the start of each oscillator cycle, the high - side mosfet turn s on, adding a positive voltage across the inductor. the c urrent in the inductor (i l ) increases until the current sense signal crosses the peak inductor current threshold that turns off the high - side mosfet and turns on the low - side mosfet . this action adds a negative voltage across the inductor, causing the inductor current to decrease. the low - side mosfet remains on for the rest of cycle. pfm mode ( adp2390 only) the adp2390 can work in pfm mode during a light load. when the comp pin voltage is below the pfm threshold voltage, the device enters pfm mode. in pfm mode, the device monitors the fb voltage to regulate the output voltage. because the high - side and low - side mosfets are turned off, the load current discharges the output capacitor , causing the output voltage to drop. when the fb voltage drops below 0.605 v, t h e device begins switching and the outpu t voltage increases as the output capacitor is charged by the inductor current. when the fb voltage exceeds 0.62 v, the device turns off both the high - side and low - side mosfets until the fb voltage drops to 0.605 v. i n the pfm mode, the output voltage ripp le is greater than the ripple in the pwm mode. precision enable/shu tdown the en input pin has a precision analog threshold of 1.2 v (typical) with 100 mv of hysteresis. when the enable pin (en) voltage exceeds 1.2 v, the regulator turns on; when it falls b elow 1.1 v (typical), the regulator turns off. to force the regulator to start automatically when input power is applied, connect the en pin to pvin. the precision en pin has an internal pull - down current source (5 a) that provides a default turn off when the en pin is open . when the en pin voltage exceeds 1.2 v (typical), the adp2389 / adp2390 are enabled and the internal pull - down current source at the en pin decreases to 1 a, which allows users to program the pvin uvlo and hysteresis. internal regulator ( vreg) the on - board regulator provides a stable supply for the internal circuits. place a 1 f , x7r or x5r ceramic capacitor between the vreg pin and gnd. the internal regulator includes a current - limit circuit to protect the output if the maximum external load current is exceeded. bootstrap circuitry the adp2389 / adp2390 include a boot strap regulator to provide the gate drive voltage for the high - side mosfet. the boot strap regulator uses differential sensing to generate a 5 v bootstrap voltage between the bst pin and the sw pin. place a 0.1 f, x 7 r or x5r ceramic capacitor between the bst pin and the sw pin. oscillator the switching frequency of the adp2389 / adp2390 (f sw ) is controlled by the rt pin. a resistor (r t ) from the rt pin to gnd can program the switching frequency according to the following equation: 12 ) (k 000 , 67 (khz) + ? = t sw r f a resistor sets the swithin freen to nd resistor sets the swithin freen to m fire shows the til reltionshi etween f sw nd r t figure 29 . switching frequency (f sw ) vs. r t 2200 2000 0 200 400 600 800 1000 1200 1400 1600 1800 10 40 70 100 130 160 190 220 250 280 310 340 switching frequency (khz) r t n 12192-029 rev. 0 | page 12 of 23
data sheet adp2389/adp2390 soft start the ss pin program s the soft start time. place a capacitor between the ss pin and gnd; an internal current charges th is capacitor to establish the soft start ramp. calculate t he soft start time using the following equation: ss ss ss i c v t = 6 . 0 where: c ss is the soft start capacitance. i ss is the soft start pull - up current (3. 4 a). if the output voltage is precharged before power - up, the adp2389 / adp2390 prevent the low - side mosfet from turning on unti l the soft start voltage exceeds the voltage on the fb pin. fast transient respo nse the adp2389 / adp2390 use the ftw pin to set the fast transient response window. place a resistor (r ftw ) between the ftw pin and gnd to program the window. calculate the window threshold using the following equation: ( ) + = ftw r threshold window if the ott olte is reter thn the settin window the fst trnsient resonse is enled the fst trnsient resonse fntion is disled if the ftw in is oen nd the ini window is to oid flse trier of the fst trnsient the window threshold st e reter thn the ott rile power good the p ower - good (pgood) pin is an active high, open - drain output that requires an external resistor to pull it up to a voltage . a logic high on the pgood pin indicates that the voltage at the fb pin (and thus the output voltage) is within 10% of the desired v alue , and there is a 16 cycle waiting period before pgood is pulled high. a logic low indicates that the voltage at the fb pin is out of 10% of the desired value , and there is a 16 - cycle waiting period before pgood is pulled low. peak current - limit and short - circuit protection the adp2389 / adp2390 have a cycle - by - cycle peak current - limit protect ion circuit to prevent current runaway. a resistor ( r ilim ) from the ilim pin to gnd program s the peak current - limit threshold according to the following equation: 0.5 ) (k 1000 (a) + ? = ilim ocp r i f tt gst s t adp adp s m f t tt w t t t ts ff t s mosfet ts t t t t t t mts g ts ss if t t t s f t fb tg fs t v ft t sft stt t ts m dg m t g s mosfet t s t t ff t ms ts m f s sft stt tms t ttmts t stt fm sft stt if t t mt ft s t sms m t ts t ts m i sm ss t t tg pvin m t s t s t tt t s t g f t tt t gt g t sft stt ss ss t gt t t m t s ss s sst t t en t gm t t tg uvlo s g sft stt tm over v oltage protection (o vp) the adp2389 / adp2390 include an ovp feature t hat protect s the regulator against an output short to a higher voltage supply or against a strong load disconnect transient. if the feedback voltage increases to 0.7 v, the internal high - side mosfet and low - side mosfet t urn off until the voltage at fb decreases to 0.63 v . a t that time, the adp2389 / adp2390 resumes normal operation. under v oltage lockout (uvlo ) the under voltage lockout (uvlo) threshold is 4.2 v with a 0.5 v hysteresis , which prevents power - on glitches from occurring. when the vin voltage rises above 4.2 v, the device e nable s and the soft start period initiates. when the vin voltage drops below 3.7 v, the device turn s off. thermal shutdown in the event that the adp2389 / adp2390 junction temperatu res rises above 150 c, the internal thermal shutdown circuit turns off the regulator for self protection. extreme junction temperatures can be the result of high current operation, poor circuit board thermal design, and/o r high ambient temperature. a 25 c hysteresis is included in the thermal shut down circuit so that if an overtemperature event occurs, the adp2389 / adp2390 does not return to normal operation until the on - chip temperature drops below 12 5 c. upon recovery, a soft start initiate s before normal operation. rev. 0 | page 13 of 23
adp2389/adp2390 data sheet applications informa tion input capacitor se lection the input decoupling capacitor attenuate s high frequency noise on the input. this capacitor must be a ceramic type in the range of 10 f to 47 f. place the capacitor close to the pvin pin. kee p t he loop composed by this input capacitor, high - side mosfet and low - side mosfet as small as possible. the voltage rating of the input capacitor must be greater than the maximum input voltage. the rms current rating of the input capacitor must be larger than the value calculated from the following equation: ( ) d d i i out rms cin C 1 _ = i out is the o utput current . d is the d uty cycle . output voltage setti ng a n external resistor divider sets t he output voltage s of the adp2389 / adp2390 . calculate t he resistor values using the following equation: ? ? ? ? ? ? ? ? + = bot top out r r v 1 6 . 0 where : r top is the top feedback resistor. r bot i s the bottom feedback resistor. to limit output voltage accuracy degradation due to fb bias current (0.1 a maximum) to less than 0.5% (maximum), ensure that r bot is less than 30 k?. table 5 gives the recommended r esistor divider for various output voltage s. table 5 . resistor divider for difference output voltage v out (v) r top , 1% (k) r bot , 1% (k) 1.0 10 15 1.2 10 10 1.5 15 10 1.8 20 10 2.5 47.5 15 3.3 10 2.21 5.0 22 3 inductor selection the inductor value is determined by the operating frequency, the input voltage, output voltage, and inductor ripple current. using a small inductor leads to a faster transient response ; however, it degrades efficiency d ue to its larger inductor r ipple current . u sing a large inductor value leads to smaller ripple current and better efficiency but results in a slower transient response. as a guideline, the inductor ripple current, i l , is typically set to one third of the maximum load current. calculate t he inductor value using the following equation: sw l out in f i d v v l ? = ) C ( where: v in is the input voltage. v out is the output voltage. d is the duty cycle. i l is the inductor ripple current . f sw is the switching frequency. in out v v d = l out peak i i i ? + = l out rms i i i ? + = table 6 . recommended inductors vendor device no. value ( h ) i sat ( a ) i rms ( a ) dcr ( m ) coilcraft xal7030 - 102me 1 21.8 16.1 4.55 xal7030 - 152me 1.5 11.9 23.5 7.6 xal7030 - 222me 2.2 10 18 13.7 toko fdue1040d - h - r22m 0.22 32 32 0.64 fdue1040d - h - r45m 0.45 27 24 1.02 fdu1040d - h - r68m 0.68 21 20 1.7 fdue1040d - h - 1r0m 1.0 18 16 2.35 fda1254 -h - 1r2m 1.2 20.2 18.4 2.6 wrth elektronik 744 333 0022 0.22 60 21.5 0.6 744 333 0047 0.47 47 20 0.8 744 333 0068 0.68 38 20 1.35 744 333 0082 0.82 36 20 1.35 744 332 0100 1.0 27.5 20 1.35 744 325 120 1.2 25 20 1.8 744 333 0150 1.5 27 18 2.5 744 333 0220 2.2 22 16 3.7 rev. 0 | page 14 of 23
data sheet adp2389/adp2390 output capacitor sel ection the output capacitor selection affects both the output ripple voltage and the loop dynamics of the regulator. during a step load transient, for instance, when the load is suddenly increased, the output capacitor supplies the load until the control loop ramp s up the inductor current. the delay caused by the control loop causes the output to undershoot. use the foll owing equation to calculate t he output capacitance required to satisfy the voltage droop requirement : ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = k uv is a factor; the typical setting is k uv = 2. i step is the load step. v out_uv is the allowable undershoot on the output voltage. w hen a load is suddenly removed from the output and the energy stored in the inductor rushes into the output capacitor, the output overshoot s . calculate t he output capacitance required to meet the overshoot requirement using the following equation : ( ) out ov out out step ov ov out v v v l i k c ? ? ? ? = _ 2 _ 2 k ov is a factor; the typical setting is k ov = 2. i step is the load step. v out_ov is the allowable overshoot on the output voltage. the output ripple is determined by the esr and the value of the capacitance. use t he following equation s to select a capacitor that can meet the output ripple requirements: ripple out sw l ripple out v f i c _ _ 8 ? ? = v out_ripple is the allowable output ripple voltage. l ripple out esr i v r ? ? = _ w here r esr is the equivalent series resistance of the output capacitor in o hms. select the largest output capacitance given by c out_uv , c out_ov , and c out_ripple to meet both load transient and output ripple performance. the selected output capacitor voltage rating m ust be greater than the output voltage. the rms current rating of the output capacitor must be greater than the value calculated using the following equation: 12 _ l rms cout i i ? = programming input vo ltage uvlo the adp2389 / adp2390 ha ve a precision enable input that program s the uvlo threshold of the input voltage, as shown in figure 30. figure 30 . programming the i nput v oltage uvlo use the following equation s to calculate r top_en and r bot_en : __ _ 1.1 v C 1.2 v 1.1 v 6.1 ? C 1.2 v 1 a in rising in falling top en vv r = v in_rising is the v in rising threshold. v in_falling is the v in falling threshold. _ _ __ 1.2 v C 6.1 ? C 1.2 v top en bot en in rising top en r r vr = compensation design for peak current mode control, the power stage can be simplified as a voltage controlled current source supplying curre n t to the output capacitor and load resistor. it is composed of one domain pole and a zero contributed by the output capacitor esr. the control to output transfer function is shown with the following equations: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = = p z vi comp out vd f s f s r a s v s v s g 2 1 2 1 ) ( ) ( ) ( g vd is the control to output transfer function. a vi = 20 a / v. r is the load resistance. f z is the zero of g vd . f p is the domain pole of g vd . out esr z c r f = 2 1 where: r esr is the equivalent series resistance of the output capacitor. c out is the output cap acitance. ( ) out esr p c r r f + = 2 1 a238 a230 1.2v 4.8a 1.3a v _ _ 1212030 rev. 0 | page 15 of 23
adp2389/adp2390 data sheet the adp2389 / adp2390 use a transconductance amplifier for the e rror amplifier and to compensate the system. figure 31 shows the simplified, peak current mode control, small signal circuit. figure 31 . si mplified p eak c urrent m ode c ontrol , s mall s ignal c ircuit the compensation components, r c and c c , contribute a zero and the optional c cp and r c contribute an optional pole. the closed - loop transfer equation is as follows: ) ( 1 1 C ) ( s g s c c c c r s s c r c c g r r r s t vd p c cp c c c c cp c m top bot bot v ? ? ? ? ? ? ? ? + + + + + = determine the cross frequency , f c . generally, f c is between f sw /12 and f sw /6. 2. calculate r c using the following equation: vi m c out out c a g f c v r = v 6 . 0 2 place the compensation zero at the domain pole , f p , and determine c c by () esr out c c rr c c r + = c cp is optional. use c cp to cancel the zero caused by the esr of the output capacitor. esr out cp c rc c r = rev. 0 | page 16 of 23
data sheet adp2389/adp2390 design example this section provides the procedures of selecting the external components based on the example specifications listed in table 7 . the schematic of this design example is shown in figure 32. table 7 . step - down dc -to - dc regulator requirements parameter specification input voltage 12.0 v 10% output voltage 1.2 v output current 12 a output voltage ripple 12 mv load transient 5%, 3 a to 9 a, 2 a/ s switching frequency 500 khz output voltage setti ng select a 10 k? resistor as the top feedback resistor (r top ) and calculate the bottom feedback resistor (r bot ) using the following equation: 0.6 0.6 bot top out rr v ?? = ?? ? ?? frequency setting use the following equation to calculate the value of r t : 67,000 (k ) C 12 (khz) t sw r f ?= inductor selection the peak - to - peak inductor ripple current, ?i l , is set to 33% of the maximum output current. use the following equation to estimate the inductor value: ( ) sw l out in f i d v v l ? = C v in = 12.0 v v out = 1.2 v d = 10% ? i l = 4 a f sw = 500 khz this results in l = 0.54 h . select the standard inductor value of 0.68 h. calculate t he peak - to - peak inductor ripple current using the following equation: ( ) sw out in l f l d v v i = ? C s ss n 3.176 a. k n n n n 2 l peak out i ii ? = + 2 2 12 l rms out i ii ? = + output capacitor sel ection the output capacitor must meet both the output voltage ripple requirement and load transient response. to meet the output voltage ripple requirement, use the following equation to calculate the esr and capac itance value of the output capacitor: ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ s ss n _ 66 f n 3.78 m. m 5 s n ns nsn mns, s n ns n ( ) out ov out out step ov ov out v v v l i k c ? ? ? ? = _ 2 _ 2 ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = k ov = k uv = 2, and are the coefficients for estimation purpose. ? i step = 6 a, and is the load transient step. ? v out_ov = 5% v out and , is the overshoot voltage. ? v out_uv = 5% v out , and is the undershoot voltage. this results in c out_ov = 332 f and c out_uv = 38 f . rev. 0 | page 17 of 23
adp2389/adp2390 data sheet according to the calculations for c out_ripple , c out_ov , and c out_uv , the output capacitance must be greater than 33 2 f and the esr of the output capacitor must be less than 3.78 m?. it is recommended that five 100 f , x5r , 6.3 v ceramic capacitors be used, such as the grm32er60j107me20 from murata , with an esr of 2 m?. compensation compone nts for be tter load transient and stability performance, set the cross frequency, f c , to f sw /10. in this case, f sw is running at 500 khz; therefore, set f c to 50 khz. the 100 f ceramic output capacitors have a derated value of 62 f. ? = = k 47 . 19 a/v 20 s 500 v 6 . 0 khz 50 f 62 5 v 2 . 1 2 c r ( ) = ? ? + ? = c c f f = ? ? = cp c choose the followin stndrd oon ents r c c c f nd c cp f soft start time prog ram the soft start feature ramps up the output voltage in a controlle d manner, eliminating output voltage overshoot during soft start, and limiting the inrush current. set the soft start time to 4 ms. 4 ms 3.4 a 22.67 nf 0.6 v 0.6 v ss ss ss ti c = = = input capacitor sele ction place a minimum 10 f ceramic capacitor near the pvin pin. in this application, one 10 f, x5r, 25 v ceramic capacitor is recommended. schematic for design example figure 32 . schematic for d esign e xample bst fb comp pgood gnd vreg rt ilim ftw ss l 0.68h c vreg 1f r t n sw pgnd en pvin vin c in 10f 25v v in = 12v c bst 0.1f c out1 100f 6.3v c out2 100f 6.3v c out3 100f 6.3v c out4 100f 6.3v c out5 100f 6.3v v out = 1.2v r top n r bot n c c 1500pf r c n c ss 22nf c cp 33pf adp2389/ adp2390 12192-032 rev. 0 | page 18 of 23
data sheet adp2389/adp2390 external components recommendation table 8 . recommended external components for typical applications with 10 a output current f sw (khz) v in (v) v out (v) l (h) c out (f) 1 r top (k) r bot (k) r c (k) c c (pf) c cp (pf) 300 12 1 0.82 680 10 15 21 2700 330 12 1.2 1 470 10 10 18 2700 270 12 1.5 1 5 100 15 10 15 2700 39 12 1.8 1.2 5 100 20 10 18 2700 33 12 2.5 1.5 3 100 47.5 15 15 2700 22 12 3.3 2.2 3 100 10 2.21 20 2700 18 12 5 2.2 100 22 3 10 2700 10 5 1 0.68 470 10 15 15 2700 330 5 1.2 0.82 470 10 10 18 2700 270 5 1.5 0.82 5 100 15 10 12 2700 39 5 1.8 1 4 100 20 10 15 2700 33 5 2.5 1 2 100 47.5 15 10 2700 22 5 3.3 1 2 100 10 2.21 12 2700 18 600 12 1.2 0.47 4 100 10 10 18 1200 27 12 1.5 0.47 3 100 15 10 18 1200 22 12 1.8 0.68 3 100 20 10 21 1200 18 12 2.5 0.82 2 100 47.5 15 20 1200 12 12 3.3 1 100 10 2.21 12 1200 10 12 5 1.2 100 22 3 20 1200 6.8 5 1 0.47 5 100 10 15 20 1200 33 5 1.2 0.47 4 100 10 10 18 1200 27 5 1.5 0.47 3 100 15 10 18 1200 22 5 1.8 0.47 2 100 20 10 14 1200 18 5 2.5 0.47 100 47.5 15 10 1200 12 5 3.3 0.47 100 10 2.21 12 1200 10 1200 12 2.5 0.47 100 47.5 15 20 680 6.8 12 3.3 0.47 47 10 2.21 12 680 4.7 12 5 0.68 47 22 3 18 680 3.3 5 1 0.13 2 100 10 15 15 680 12 5 1.2 0.24 2 100 10 10 18 680 12 5 1.5 0.24 2 100 15 10 22.1 680 10 5 1.8 0.24 100 20 10 14 680 8.2 5 2.5 0.24 47 47.5 15 9.1 680 6.8 5 3.3 0.24 47 10 2.21 12 680 4.7 1 680 f: 6.3 v, kemet t530x687m006ate010 ; 470 f: 6.3 v, kemet t520x477m006ate010; 100 f: 6.3 v, x5r, murata grm32er60j107me20; 47 f: 6.3 v, x5r, murata grm32er60j476me20 . rev. 0 | page 19 of 23
adp2389/adp2390 data sheet rev. 0 | page 20 of 23 circuit board layout recommendations good printed circuit board (pcb) layout is essential for obtaining the best performance from the adp2389 / adp2390 . poor pcb layout can degrade the output regulation, as well as the emi and electromagnetic compatibility (emc) performance. figure 34 shows an example of a good pcb layout for the adp2389 / adp2390 . for optimum layout, refer to the following guidelines: ? use separate analog ground planes and power ground planes. connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to the analog ground. in addition, connect the ground reference of power components, such as input and output capacitors, to power ground. connect both ground planes to the exposed gnd pad of the adp2389 / adp2390 . ? place the input capacitor, the inductor, and the output capacitor as close as possible to the ic, and use short traces. ? ensure that the high current loop traces are as short and as wide as possible. make the high current path from the input capacitor through the inductor, the output capacitor, and the power ground plane back to the input capacitor as short as possible. to accomplish this, ensure that the input and output capacitors share a common power ground plane. in addition, ensure that the high current path from the power ground plane through the inductor and output capacitor back to the power ground plane is as short as possible by tying the pgnd pins of the adp2389 / adp2390 to the pgnd plane as close as possible to the input and output capacitors. ? connect the exposed gnd pad of the adp2389 / adp2390 to a large, external copper ground plane to maximize its power dissipation capability and minimize junction temperature. in addition, connect the exposed sw pad to the sw pins of the adp2389 / adp2390 , using short, wide traces, or connect the exposed sw pad to a large copper plane of the switching node for high current flow to reduce thermal resistance. ? place the feedback resistor divider network as close as possible to the fb pin to prevent noise pickup. minimize the length of the trace that connects the top of the feedback resistor divider to the output while keeping the trace away from the high current traces and the switching node to avoid noise pickup. to reduce noise pickup further, place an analog ground plane on either side of the fb trace and ensure that the trace is as short as possible to reduce the parasitic capacitance pickup. figure 33. high current path in the pcb circuit bst fb comp pgood gnd vreg rt ilim ftw ss l c vreg r t r ilim r ftw sw pgnd en pvin vin c in v in c bst c out v out r top r bot c c r c c ss adp2389/ adp2390 c cp 12192-033 notes 1. items in gray indicates high current.
data sheet adp2389/adp2390 rev. 0 | page 21 of 23 figure 34. recommended pcb layout comp ss pgood rt ilim en fb sw vreg gnd sw sw sw sw pgnd pgnd pgnd pgnd pgnd pgnd sw bst pvin pvin pvin pvin gnd sw r top analog ground plane r bot r c c cp c c r t power ground plane vout pvin sw c vreg c bst inductor output capacitor bottom layer trace via copper plane r ilim pgnd sw sw pvin vin c ss ftw r ftw input bypass capacitor input bulk capacitor 12192-034
adp2389/adp2390 data sheet typical appli cation circuits figure 35 through figure 37 show some typical application circuits of the adp2389 / adp 2390 for user information . figure 35 . v in = 12 v, v out = 3.3 v, i out = 12 a, f sw = 600 khz with pfm m ode figure 36 . v in = 12 v, v out = 1.2 v, i out = 8 a, f sw = 500 khz with p rogrammable c urrent l imit figure 37 . v in = 12 v, v out = 1.8 v, i out = 12 a, f sw = 600 khz with f ast t ransient bst fb comp pgood gnd vreg rt ilim ftw ss l 1.2h c vreg 1f r t 100k sw pgnd en pvin vin c in 10f 25v v in 12v c bst 0.1f c out2 100f 6.3v c out3 100f 6.3v c out1 100f 6.3v v out 3.3v, 12a r top 10k r bot 2.21k c c 1500pf r c 38.3k c ss 22nf adp2390 c cp 10pf 12192-035 bst fb comp pgood gnd vreg rt ilim ftw ss l 1h c vreg 1f r t 121k r ilim 82.5k sw pgnd en pvin vin c in 10f 25v v in 12v c bst 0.1f c out2 10f 6.3v c out1 330f 16v v out 1.2v, 8a r top 10k r bot 10k c c 2200pf r c 21k c ss 22nf adp2389 c cp 100pf 12192-036 bst fb comp pgood gnd vreg rt ilim ftw ss l 0.68h c vreg 1f r t 100k r ftw 78.7k sw pgnd en pvin vin c in 10f 25v v in 12v c bst 0.1f c out2 100f 6.3v c out3 100f 6.3v c out4 100f 6.3v c out1 100f 6.3v v out 1.8v, 12a r top 20k r bot 10k c c 1200pf r c 27k c ss 22nf adp2389 c cp 22pf 12192-037 rev. 0 | page 22 of 23
data sheet adp2389/adp2390 rev. 0 | page 23 of 23 outline dimensions figure 38. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-19) dimensions shown in millimeters ordering guide model 1 temperature range output voltage package description package option adp2389acpz-r7 ?40c to +125c adjustable 32-lead lead frame chip scale package [lfcsp_vq] cp-32-19 adp2390acpz-r7 ?40c to +125c adjustable 32-lead lead frame chip scale package [lfcsp_vq] cp-32-19 adp2389-evalz evaluation board ADP2390-EVALZ evaluation board 1 z = rohs compliant part. 1.777 1.677 1.527 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.152 ref 0.425 0.625 0.984 coplanarity 0.08 0.30 0.25 0.20 5.10 5.00 sq 4.90 1.00 0.90 0.80 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.35 0.25 12-12-2012-a compliant to jedec standards mo-220-vhhd 3.80 3.70 3.55 3.441 3.341 3.191 1.725 1.625 1.475 exposed pad exposed pad 0.65 0.65 ?2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12192-0-8/15(0)

▲Up To Search▲

Price & Availability of ADP2390-EVALZ

	To Download ADP2390-EVALZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .